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Applications

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"Memristor storage devices "


PSFL: Applications

Brief examples of a few applications (some undertaken and some not) to illustrate the potential of PSFL technology and its benefits over standard photolithography for end-users include (but are not limited to):

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Transparent conductors

Examples of typical low temperature physical vapour deposited (PVD) transparent conductors include ITO, AZO, and GZO. Applications for transparent conductors is diverse, with a few examples being:

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  • Transparent circuits [e.g., Interconnections]

  • Photonic devices [e.g., Electrical contacts]

  • Automobile and building glazing [e.g., Optical antennas, transparent heater zones, invisible circuitry]

  • Sensor and transducers [e.g., Micro heaters]

  • Displays [e.g., Touch and slider switches]

  • Electronic windows [e.g., Liquid crystal layer light valve switching]

 

Amorphous metal-oxide thin film transistors

As the performance of amorphous metal oxide thin film transistors continues to improve more and more diverse electronics applications fall within its reach. Numerous investigations are underway globally aimed at leveraging the best out of the more prominent oxide-based TFT device structures that include substrate bottom-top contact, top gate top-contact, inverted-staggered bottom gate-top contact, inverted-staggered top gate, coplanar bottom gate, coplanar top gate, and vertical (V) based on the needs of the applications being considered.

There are generally two types of process that are in use, namely, back-channel etch (BCE) and etch-stop layer (ESL). However, it is possible to consider an alternate approach that does not pattern deposition apertures in a mask on the sample surface or use etching for patterning whole area thin films that form a TFT. This alternate approach is called peelable solid film lithography (PSFL). 3t’s PSFL technology allows the as-deposited thin films to be patterned directly after deposition by mechanically peeling off the solid film aperture-patterned mask taking the residual coating with it, to leave the required patterned single layer, or auto-aligned multiple-layer stack, coating on the sample.

Top gate TFT 3D illustration.jpg

A basic top gate device configuration is shown in the illustration on the left, which can be produced using 2 or 3 pattern-aligned PSFL film masking steps. More complex designs that incorporate (1) advanced interlayer dielectric (ILD) and (2) semiconductor growth control can also be manufactured using suitably designed PSFL masks.

PSFL technology can support roll-to-roll and roll-to-plate mask attachment and can be scaled to larger substrate areas

Metal-oxide thin film memory

The ability to store information rapidly is vital for advanced access cloud computing, data mining, machine learning, the internet of things (IoT), and artificial intelligence (AI), amongst others. One example of such storage technology that is actively being developed is Resistive Random Access Memory (ReRAM or memristor), a non-volatile memory.

 

For ReRAM device development, many physical vapour deposition (PVD) metal oxides have been investigated, as exemplified by the wealth of public domain articles that have been published by industry and academia. The metal oxide coating schemes investigated are based on single layer or nano-stacked multilayer structures using two-terminal capacitor type Metal-Insulator-Metal (M-I-M) device structures that include inorganic binary and ternary metal oxide coatings such as Al2O3, HfO2, Co3O4, Ga-Sn-O, and perovskites with various metal contacts based on for example Al, ITO, Ti, Au, and TiN.

Simple MIM device cross section illustration.jpg

PSFL technology is ideally suited to patterning PVD metals and metal oxides at low deposition temperature using its direct deposition peel-to-reveal approach.

SM-OLED display pixels

Using an early variant of PSFL film masking, high resolution small-molecule organic light-emitting diode (SM-OLED) single colour icons were directly patterned from a vacuum-based vapour that showed well-defined patterned feature edge definition for an aperture resolution more than 1,000 dpi.

 

This limited trial work demonstrated:

  • SM-OLED vacuum vapour coating patterning of feature size < 20 micron

  • Film mask compatibility with the deposition of auto-aligned organic nano stack patterning

  • Film mask compatibility with high vacuum (> 2x10-6 torr)

  • Film mask compatibility with thermal evaporation of organic small molecule material

 

The laminated mask peel off removal was achieved without affecting previously processed device layers.

Additional possible applications for PSFL patterned thin film coatings

Examples of other possible thin film device applications where PSFL sheet film masking technology has the potential to provide manufacturing advantages include:

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  • Electro-wetting-on-dielectric (EWOD) coplanar electrode array for droplet actuation in biological and chemical microfluidic devices

  • Fusible links and programmable electrically configurable logic arrays

  • Interdigitated electrodes (IDE) for surface acoustic wave devices or thin film memory devices

  • Nanolaminate stack metal contacts with aligned intermetal barrier

  • Organic evaporated coatings for device applications such as flat panel/flexible display pixels and thin film transistor switching arrays

  • Porous metal oxide semiconductors for gas sensing devices

  • PZT thin film islands for use in ultrasonic device actuators

  • Surface mount resistor, capacitor, inductor components

  • Thin film conductivity measurement cell electrical contact metallisation [Transmission line, etc.]

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